RUN crchalf_ocn.ocn
CLK rate can be changed via Tclk in crchalf_ocn.ocn
Vdd can be changed via pvdd in crchalf_ocn.ocn
The data and key input could be altered in the netlist file with Vdd and Vss representting 1 and 0


For outputs

CLK is clock signal.

EN is CRCHalf enable signal, which turns high after the first clock cycle.

sout_15 to sout_0 represents data output from the most significant bit to less significant bit, which has a valid value at the end of the 10th clock cycle.

i("V0:p") is the transient current going through VDD supply.

The avarage current of i("V0:p") is recorded in output.txt file
